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ALC260/ALC260D
2 CHANNEL HIGH DEFINITION AUDIO CODEC DATASHEET
Rev. 1.3 03 March 2005 Track ID: JATR-1076-21
ALC260(D) Datasheet
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DISCLAIMER Realtek provides this document "as is", without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.
TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT This document is intended for the hardware and software engineer's general information on the Realtek ALC260(D) audio codec chip. Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision 1.0 1.1 1.2 Release Date 2004/07/20 2004/09/29 2004/11/08 Summary Preliminary release. First official release. Add HDA 1.0 compliant part number (Table 83, page 72). Updated to reflect modifications in ALC260, ALC260-VD, ALC260-VD-LF, ALC260-VE, ALC260-VE-LF. 1. Power-Off CD mode supported only in ALC260 & ALC260-LF. 2. Parameter `subsystem ID' is read as 0s (Table 19, page 19). 3. Verb `subsystem verb' is supported (Table 73, page 62, and Table 74, page 63). Add lead (Pb)-free and version package identification information on page 5 and in Table 83, on page 72. Add new versions with Dolby(R) Digital Live (see Table 83, page 72).
1.3
2005/03/03
2 Channel High Definition Audio Codec
ii
Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
Table of Contents
1. 2. GENERAL DESCRIPTION ......................................................................................................................................1 FEATURES .................................................................................................................................................................2
2.1. 2.2.
3. 4.
HARDWARE FEATURES.....................................................................................................................2 SOFTWARE FEATURES ......................................................................................................................3
SYSTEM APPLICATIONS .......................................................................................................................................3 BLOCK DIAGRAM ...................................................................................................................................................4
4.1. 4.2.
5.
BLOCK DIAGRAM .............................................................................................................................4 ANALOG INPUT/OUTPUT UNIT .........................................................................................................4
PIN ASSIGNMENTS..................................................................................................................................................5
5.1.
6.
LEAD (PB)-FREE PACKAGE AND VERSION IDENTIFICATION .............................................................5
PIN DESCRIPTIONS .................................................................................................................................................6
6.1. 6.2. 6.3. 6.4.
7.
DIGITAL I/O PINS .............................................................................................................................6 ANALOG I/O PINS.............................................................................................................................6 FILTER/REFERENCE ..........................................................................................................................7 POWER/GROUND ..............................................................................................................................7
HIGH DEFINITION AUDIO LINK PROTOCOL..................................................................................................8
7.1.
7.1.1. 7.1.2.
LINK SIGNALS ..................................................................................................................................8
Signal Definitions ...................................................................................................................................................9 Signaling Topology...............................................................................................................................................10
7.2.
7.2.1. 7.2.2. 7.2.3.
FRAME COMPOSITION.....................................................................................................................11
Outbound Frame - Single SDO............................................................................................................................11 Inbound Frame - Single SDI ................................................................................................................................12 Variable Sample Rates .........................................................................................................................................13
7.3.
7.3.1. 7.3.2. 7.3.3.
RESET AND INITIALIZATION............................................................................................................14
Link Reset .............................................................................................................................................................15 Codec Reset ..........................................................................................................................................................16 Codec Initialization Sequence ..............................................................................................................................16
7.4.
7.4.1. 7.4.2.
VERB AND RESPONSE FORMAT.......................................................................................................17
Command Verb Format........................................................................................................................................17 Response Format..................................................................................................................................................17
7.5.
8.
POWER MANAGEMENT ...................................................................................................................18
SUPPORTED VERBS AND PARAMETERS ........................................................................................................19
8.1.
8.1.1. 8.1.2. 8.1.3. 8.1.4. 8.1.5. 8.1.6. 8.1.7. 8.1.8.
VERB - GET PARAMETERS (VERB ID=F00H) .................................................................................19
Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................19 Parameter - Subsystem ID (Verb ID=F00h, Parameter ID=01h).......................................................................19 Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................20 Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) .....................................................20 Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) ..........................................................21 Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) ...............................................21 Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ..................................................22 Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ................................................23 iii Track ID: JATR-1076-21 Rev. 1.3
2 Channel High Definition Audio Codec
ALC260(D) Datasheet
8.1.9. 8.1.10. 8.1.11. 8.1.12. 8.1.13. 8.1.14. 8.1.15. 8.1.16. 8.1.17. Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) .................................................25 Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................25 Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) ...............................26 Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) .............................27 Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh)............................................................27 Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh) ......................................................28 Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h).......................................................28 Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)...............................................................29 Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) ..................................................29
8.2. 8.3. 8.4. 8.5. 8.6. 8.7. 8.8. 8.9. 8.10. 8.11. 8.12. 8.13. 8.14. 8.15. 8.16. 8.17. 8.18. 8.19. 8.20. 8.21. 8.22. 8.23. 8.24. 8.25. 8.26. 8.27. 8.28. 8.29. 8.30. 8.31. 8.32. 8.33. 8.34. 8.35. 8.36. 8.37. 8.38.
VERB - GET CONNECTION SELECT CONTROL (VERB ID=F01H) ....................................................30 VERB - SET CONNECTION SELECT (VERB ID=701H) .....................................................................32 VERB - GET CONNECTION LIST ENTRY (VERB ID=F02H) .............................................................32 VERB - GET COEFFICIENT INDEX (VERB ID=DH) ..........................................................................38 VERB - SET COEFFICIENT INDEX (VERB ID=5H) ...........................................................................38 VERB - GET PROCESSING COEFFICIENT (VERB ID=CH) ................................................................39 VERB - SET PROCESSING COEFFICIENT (VERB ID=4H)..................................................................39 VERB - GET AMPLIFIER GAIN (VERB ID=BH) ...............................................................................40 VERB - SET AMPLIFIER GAIN (VERB ID=3H).................................................................................42 VERB - GET CONVERTER FORMAT (VERB ID=AH)........................................................................43 VERB - SET CONVERTER FORMAT (VERB ID=2H) .........................................................................44 VERB - GET POWER STATE (VERB ID=F05H)................................................................................44 VERB - SET POWER STATE (VERB ID=705H).................................................................................45 VERB - GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...................................................46 VERB - SET CONVERTER STREAM, CHANNEL (VERB ID=706H)....................................................46 VERB - GET PIN WIDGET CONTROL (VERB ID=F07H) ..................................................................47 VERB - SET PIN WIDGET CONTROL (VERB ID=707H) ...................................................................48 VERB - GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...............................................49 VERB - SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ................................................50 VERB - GET PIN SENSE (VERB ID=F09H)......................................................................................50 VERB - EXECUTE PIN SENSE (VERB ID=709H)..............................................................................51 VERB - GET CONFIGURATION DEFAULT (VERB ID=F1CH) ...........................................................51 VERB - SET CONFIGURATION DEFAULT BYTES 0 ~ 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0 ~ 3) ..................................................................................................................................52 VERB - GET BEEP GENERATOR (VERB ID=F0AH).......................................................................52 VERB - SET BEEP GENERATOR (VERB ID=70AH)........................................................................53 VERB - GET GPIO DATA (VERB ID= F15H)..................................................................................53 VERB - SET GPIO DATA (VERB ID= 715H) ..................................................................................54 VERB - GET GPIO ENABLE MASK (VERB ID= F16H) ...................................................................54 VERB - SET GPIO ENABLE MASK (VERB ID=716H) .....................................................................55 VERB - GET GPIO DIRECTION (VERB ID=F17H) ..........................................................................55 VERB - SET GPIO DIRECTION (VERB ID=717H) ...........................................................................56 VERB - GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ............................56 VERB - SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..............................57 VERB - FUNCTION RESET (VERB ID=7FFH) ..................................................................................57 VERB - GET DIGITAL CONVERTER CONTROL (VERB ID= F0DH) ..................................................58 VERB - SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ...............59 VERB - GET/SET EAPD ENABLE (VERB ID= F0CH/70CH) ...........................................................61
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2 Channel High Definition Audio Codec
ALC260(D) Datasheet
8.39. GET/SET VOLUME KNOB WIDGET (NID=1BH) (VERB ID= F0FH/70FH).......................................62 8.40. VERB - GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H) ......................................62 8.41. VERB - SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0])...................63
9. CHARACTERISTICS ..............................................................................................................................................64
9.1.
9.1.1. 9.1.2. 9.1.3. 9.1.4.
DC CHARACTERISTICS ...................................................................................................................64
Absolute Maximum Ratings ..................................................................................................................................64 Threshold Voltage ................................................................................................................................................64 Digital Filter Characteristics ...............................................................................................................................65 S/PDIF Input/Output Characteristics...................................................................................................................65
9.2.
9.2.1. 9.2.2. 9.2.3. 9.2.4.
AC CHARACTERISTICS ...................................................................................................................66
Link Reset and Initialization Timing ....................................................................................................................66 Link Timing Parameters at the Codec ..................................................................................................................67 S/PDIF Output and Input Timing .........................................................................................................................68 Test Mode .............................................................................................................................................................68
9.3.
10. 11. 12.
ANALOG PERFORMANCE ................................................................................................................69
APPLICATION CIRCUITS ....................................................................................................................................70 MECHANICAL DIMENSIONS ..............................................................................................................................71 ORDERING INFORMATION ................................................................................................................................72
List of Tables
TABLE 1. DIGITAL I/O PINS ..........................................................................................................................................................6 TABLE 2. ANALOG I/O PINS..........................................................................................................................................................6 TABLE 3. FILTER/REFERENCE .......................................................................................................................................................7 TABLE 4. POWER/GROUND ...........................................................................................................................................................7 TABLE 5. LINK SIGNAL DEFINITIONS ............................................................................................................................................9 TABLE 6. HDA SIGNAL DEFINITIONS ...........................................................................................................................................9 TABLE 7. DEFINED SAMPLE RATE AND TRANSMISSION RATE.....................................................................................................13 TABLE 8. 48KHZ VARIABLE RATE OF DELIVERY TIMING ...........................................................................................................13 TABLE 9. 44.1KHZ VARIABLE RATE OF DELIVERY TIMING ........................................................................................................14 TABLE 10. 40-BIT COMMANDS IN 4-BIT VERB FORMAT ...............................................................................................................17 TABLE 11. 40-BIT COMMANDS IN 12-BIT VERB FORMAT .............................................................................................................17 TABLE 12. SOLICITED RESPONSE FORMAT....................................................................................................................................17 TABLE 13. UNSOLICITED RESPONSE FORMAT ...............................................................................................................................17 TABLE 14. SYSTEM POWER STATE DEFINITIONS...........................................................................................................................18 TABLE 15. POWER CONTROLS IN NID IS 01H, 02H~05H, 07H~09H ..............................................................................................18 TABLE 16. POWERED DOWN CONDITIONS ....................................................................................................................................18 TABLE 17. VERB - GET PARAMETERS (VERB ID=F00H) ..............................................................................................................19 TABLE 18. PARAMETER - VENDOR ID (VERB ID=F00H, PARAMETER ID=00H) ..........................................................................19 TABLE 19. PARAMETER - SUBSYSTEM ID (VERB ID=F00H, PARAMETER ID=01H) .....................................................................19 TABLE 20. PARAMETER - REVISION ID (VERB ID=F00H, PARAMETER ID=02H) .........................................................................20 TABLE 21. PARAMETER - SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H) ................................................20 2 Channel High Definition Audio Codec v Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
TABLE 22. PARAMETER - FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H)........................................................21 TABLE 23. PARAMETER - AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H)...........................................21 TABLE 24. PARAMETER - AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H) ..............................................22 TABLE 25. PARAMETER - SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH) ............................................23 TABLE 26. PARAMETER - SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH)............................................25 TABLE 27. PARAMETER - PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH).................................................................25 TABLE 28. PARAMETER - AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMP PARAMETER ID=0DH) ..................................26 TABLE 29. PARAMETER - AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMP PARAMETER ID=12H)...............................27 TABLE 30. PARAMETER - CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH)........................................................27 TABLE 31. PARAMETER - SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH) .................................................28 TABLE 32. PARAMETER - PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H) ...................................................28 TABLE 33. PARAMETER - GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H) .............................................................29 TABLE 34. PARAMETER - VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H) ..............................................29 TABLE 35. VERB - GET CONNECTION SELECT CONTROL (VERB ID=F01H) .................................................................................30 TABLE 36. VERB - SET CONNECTION SELECT (VERB ID=701H)...................................................................................................32 TABLE 37. VERB - GET CONNECTION LIST ENTRY (VERB ID=F02H)...........................................................................................32 TABLE 38. VERB - GET COEFFICIENT INDEX (VERB ID=DH) .......................................................................................................38 TABLE 39. VERB - SET COEFFICIENT INDEX (VERB ID=5H).........................................................................................................38 TABLE 40. VERB - GET PROCESSING COEFFICIENT (VERB ID=CH)..............................................................................................39 TABLE 41. VERB - SET PROCESSING COEFFICIENT (VERB ID=4H) ...............................................................................................39 TABLE 42. VERB - GET AMPLIFIER GAIN (VERB ID=BH).............................................................................................................40 TABLE 43. VERB - SET AMPLIFIER GAIN (VERB ID=3H)..............................................................................................................42 TABLE 44. VERB - GET CONVERTER FORMAT (VERB ID=AH) .....................................................................................................43 TABLE 45. VERB - SET CONVERTER FORMAT (VERB ID=2H) ......................................................................................................44 TABLE 46. VERB - GET POWER STATE (VERB ID=F05H) .............................................................................................................44 TABLE 47. VERB - SET POWER STATE (VERB ID=705H)..............................................................................................................45 TABLE 48. VERB - GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ................................................................................46 TABLE 49. VERB - SET CONVERTER STREAM, CHANNEL (VERB ID=706H) .................................................................................46 TABLE 50. VERB - GET PIN WIDGET CONTROL (VERB ID=F07H)................................................................................................47 TABLE 51. VERB - SET PIN WIDGET CONTROL (VERB ID=707H).................................................................................................48 TABLE 52. VERB - GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H).............................................................................49 TABLE 53. VERB - SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) .............................................................................50 TABLE 54. VERB - GET PIN SENSE (VERB ID=F09H) ...................................................................................................................50 TABLE 55. VERB - EXECUTE PIN SENSE (VERB ID=709H) ...........................................................................................................51 TABLE 56. VERB - GET CONFIGURATION DEFAULT (VERB ID=F1CH).........................................................................................51 TABLE 57. VERB - SET CONFIGURATION DEFAULT BYTES 0 ~ 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0 ~ 3) ...........52 TABLE 58. VERB - GET BEEP GENERATOR (VERB ID= F0AH) ...................................................................................................52 TABLE 59. VERB - SET BEEP GENERATOR (VERB ID= 70AH) ....................................................................................................53 TABLE 60. VERB - GET GPIO DATA (VERB ID= F15H) ...............................................................................................................53 TABLE 61. VERB - SET GPIO DATA (VERB ID= 715H)................................................................................................................54 TABLE 62. VERB - GET GPIO ENABLE MASK (VERB ID= F16H).................................................................................................54 TABLE 63. VERB - SET GPIO ENABLE MASK (VERB ID=716H)...................................................................................................55 TABLE 64. VERB - GET GPIO DIRECTION (VERB ID=F17H)........................................................................................................55 TABLE 65. VERB - SET GPIO DIRECTION (VERB ID=717H).........................................................................................................56 TABLE 66. VERB - GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ..........................................................56 TABLE 67. VERB - SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) ...........................................................57 TABLE 68. VERB - FUNCTION RESET (VERB ID=7FFH) ...............................................................................................................57 TABLE 69. VERB - GET DIGITAL CONVERTER CONTROL (VERB ID= F0DH)................................................................................58 TABLE 70. VERB - SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH).............................................59 TABLE 71. VERB - GET/SET EAPD ENABLE (VERB ID= F0CH/70CH) ........................................................................................61 TABLE 72. GET/SET VOLUME KNOB WIDGET (NID=21H) (VERB ID= F0FH/70FH).....................................................................62 TABLE 73. VERB - GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H) ....................................................................62 TABLE 74. VERB - SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR [7:0])...............................................63 TABLE 75. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................64 2 Channel High Definition Audio Codec vi Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
TABLE 76. THRESHOLD VOLTAGE ................................................................................................................................................64 TABLE 77. DIGITAL FILTER CHARACTERISTICS ............................................................................................................................65 TABLE 78. S/PDIF INPUT/OUTPUT CHARACTERISTICS .................................................................................................................65 TABLE 79. LINK RESET AND INITIALIZATION TIMING ...................................................................................................................66 TABLE 80. LINK TIMING PARAMETERS AT THE CODEC .................................................................................................................67 TABLE 81. S/PDIF OUTPUT AND INPUT TIMING ...........................................................................................................................68 TABLE 82. ANALOG PERFORMANCE..............................................................................................................................................69 TABLE 83. ORDERING INFORMATION ............................................................................................................................................72
List of Figures
FIGURE 1. BLOCK DIAGRAM .........................................................................................................................................................4 FIGURE 2. ANALOG INPUT/OUTPUT UNIT .....................................................................................................................................4 FIGURE 3. PIN ASSIGNMENTS........................................................................................................................................................5 FIGURE 4. HDA LINK PROTOCOL .................................................................................................................................................8 FIGURE 5. BIT TIMING...................................................................................................................................................................9 FIGURE 6. SIGNALING TOPOLOGY...............................................................................................................................................10 FIGURE 7. SDO OUTBOUND FRAME............................................................................................................................................11 FIGURE 8. SDO STREAM TAG IS INDICATED IN SYNC ...............................................................................................................11 FIGURE 9. SDI INBOUND STREAM...............................................................................................................................................12 FIGURE 10. SDI STREAM TAG AND DATA.....................................................................................................................................12 FIGURE 11. LINK RESET TIMING ...................................................................................................................................................15 FIGURE 12. CODEC INITIALIZATION SEQUENCE ............................................................................................................................16 FIGURE 13. LINK RESET AND INITIALIZATION TIMING ..................................................................................................................66 FIGURE 14. LINK SIGNALS TIMING................................................................................................................................................67 FIGURE 15. INPUT AND OUTPUT TIMING .......................................................................................................................................68
2 Channel High Definition Audio Codec
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ALC260(D) Datasheet
1.
General Description
The ALC260 and ALC260D* 2-Channel High Definition Audio (HDA) Codecs with UAA (Universal Audio Architecture), featuring a 24-bit two-channel DAC and two stereo 20-bit ADCs, are designed for commercial Desktop and Notebook PC systems. The codecs incorporate proprietary converter technology to achieve 95dB sound quality; easily meeting PC2001 requirements and also bringing PC sound quality closer to consumer electronic devices. The ALC260(D) provides 2 output channels, along with flexible mixing, mute, and fine gain control functions to provide a complete integrated audio solution for PCs. The DAC (with a highest sampling frequency of 192kHz) and Realtek proprietary hardware content protection are applicable for DVD-Audio; previously only implemented in high-end consumer electronics but now achieved by PCs equipped with the ALC260(D). The ALC260(D) provides high-quality audio using S/PDIF to output analog data, or for multiple-source recording applications. Realtek's proprietary impedance sensing and jack detect techniques allow device loads on inputs and outputs to be auto-detected. All analog IO are input and output capable, headphone amplifiers are also integrated at each analog output. All analog IOs can be re-tasked according to user's definitions, or automatically switched depending on the connected device type (Universal Audio Jack(R)). The ALC260(D) supports 32-bit S/PDIF input and output functions and a sampling rate of up to 96kHz, offering easy connection of PCs to high-quality consumer electronic products such as AC-3 decoders/speakers, and mini disk devices. The ALC260(D) supports host/soft audio from the Intel ICH6 chipset, and also from any other HDA compatible audio controller. With power management setting, Realtek's unique microphone application (AEC/Beam Forming/Noise Suppression), optional Dolby(R) Digital Live, and reliable driver support, the ALC260(D) is the ideal choice for Commercial Desktop and Notebook PC users.
Note: `D' directly after ALC260 indicates Dolby Digital Live (software feature). See Table 83, page 72.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
2.
2.1.
Features
Hardware Features
Single-chip multi-bit Sigma-Delta converters with high S/N ratio 1 stereo DAC supports 16/20/24-bit PCM format with 44.1/48/96/192kHz sample rate 2 stereo ADCs support 16/20-bit PCM format with 44.1/48/96kHz sample rate Applicable for 2-Channel 192kHz DVD-Audio solutions LINE-OUT, HP-OUT, LINE1, LINE2, MIC1, and MIC2 are stereo input and output re-tasking MONO line level output to subwoofer speaker for 2.1 channel applications High-quality differential CD analog input External PCBEEP input is applicable, and internal BEEP generator is integrated Power-Off CD mode supported (Only in ALC260 & ALC260-LF) Power management and enhanced power saving features Power support: Digital: 3.3V; Analog: 3.3V/5.0V Selectable 2.5V/3.75V VREFOUT Two jack detection pins (each designed to detect 4 jacks) Supports 44.1/48/96/192kHz S/PDIF output Supports 44.1/48/96kHz S/PDIF input 48-pin LQFP packages (lead (Pb)-free packages also available) Supports external volume knob control External PCBEEP Pass-Through when link is in RESET state (Not supported in the ALC260(D)-VE and ALC260(D)-VE-LF) Reserve analog mixer architecture is backwards compatible with AC'97 -64dB ~ +30dB with 1dB mixer gain resolution for finer volume control Impedance sensing capability for each re-tasking jack Built-in headphone amplifier for each re-tasking jack Supports external volume knob control Supports GPIO (General Purpose Input/Output) for customized applications Hardware copyright protection for DVD-Audio
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
2.2.
Software Features
Meets Microsoft WHQL/WLP 2.0 audio requirements EAXTM 1.0 & 2.0 compatible Direct Sound 3DTM compatible A3DTM compatible I3DL2 compatible HRTF 3D Positional Audio Emulation of 26 sound environments to enhance gaming experience 10-band Software Equalizer Voice Cancellation and Key Shifting in Karaoke mode Realtek Media Player Enhanced Configuration Panel and device sensing wizard to improve user experience Content Copy Protection for S/PDIF interface Power Management setting Microphone Acoustic Echo Cancellation (AEC) and Beam Forming (BF) technology for voice application Mono/Stereo Microphone Noise Suppression ALC260D, ALC260D-LF, ALC260D-VE, and ALC260D-VE-LF feature Dolby(R) Digital Live
3.
System Applications
Multimedia PCs 3D PC Games Information Appliances (IA) Voice Recognition Audio Conferencing
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
4.
4.1.
Block Diagram
Block Diagram
ALC260(D) - High Definition Audio (HDA) Codec
0Ah M M 02h M M SRC DAC M M /2 VOL 09h VOL VOL 08h M 11h
Out
10h
MONO-OUT
LOUT2 LOUT1
M M
In/Out
0Fh
HP-OUT-L/R LINE-OUT-L/R
RESET# BITCLK SYNC SDOUT SDIN
In/Out
07h VOL VOL VOL VOL VOL VOL VOL VOL
HDA Link Interface
MMMMMM 05h SRC ADC G M
MM
BEEP Gen.
PCBEEP
17h 16h
CD-L / R / GND
LOUT1 LOUT2 M
In/Out
LINE2-L / R,VREFO
15h
04h SRC ADC G M
LOUT1 LOUT2
M
In/Out
LINE1-L / R,VREFO
14h
LOUT1 LOUT2
M
In/Out
MIC2-L/R,VREFO
13h
: Stereo Analog : Stereo Digital VOL: Analog Volume M: Analog Mute
1
Parameters
03h
LOUT1 LOUT2
M
In/Out
MIC1-L/R,VREFO S/PDIF-OUT S/PDIF-IN
18h
12h
1Ah
Vendor Regs.
06h
19h
Jack Detection
JD1 (Sense A) JD2 (Sense B) DCVOL
1Bh
Figure 1. Block Diagram
4.2.
Analog Input/Output Unit
R A EN_OBUF EN_AMP EN_OBUF
Pin complex widgets NID=0Fh, 10h, 12h, 13h, 14h, and 15h are re-tasking IOs.
Left Right
Output_Signal_Left Output_Signal_Right Input_Signal_Left Input_Signal_Right
R
EN_IBUF
Figure 2. Analog Input/Output Unit
2 Channel High Definition Audio Codec
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ALC260(D) Datasheet
5.
Pin Assignments
LINE-OUT-R LINE-OUT- L Sense B DCVOL MIC1-VREFO-R LINE2-VREFO MIC2-VREFO LINE1-VREFO-L MIC1-VREFO-L VREF AVSS1 AVDD1
36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 ALC260(D) 42 43 44 45 LLLLLLL TXXXV 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 2 0
MONO-OUT AVDD2 HP-OUT-L JDREF HP-OUT-R AVSS2 GPIO0 GPIO1 NC NC SPDIFI/EAPD SPDIFO
LINE1-R LINE1-L MIC1-R MIC1-L CD-R CD-GND CD-L MIC2-R MIC2-L LINE2-R LINE2-L Sense A
Note: JDREF is used to calibrate reference current for jack detection.
5.1. Lead (Pb)-Free Package and Version Identification
Lead (Pb)-free package is indicated by an "L" in the location marked "T" in Figure 3. The version number is shown in the location marked "V".
2 Channel High Definition Audio Codec
DVDD1 GPIO2 GPIO3 DVSS1 SDATA-OUT BIT- C LK DVSS2 SDATA-IN DVDD2 SYNC RESET# PCBEEP
Figure 3. Pin Assignments 5 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
6.
6.1.
Pin Descriptions
Digital I/O Pins
Type I I I I O I/O O I/O I/O I/O I/O Pin # 11 10 6 5 8 47 48 43 44 2 3 Table 1. Digital I/O Pins Description Characteristic Definition H/W reset Schmitt trigger input, VIL=1.0V, VIH=2.0V Sample Sync (48kHz) Schmitt trigger input, VIL=1.0V, VIH=2.0V 24MHz Bit clock input Schmitt trigger input, VIL=1.0V, VIH=2.0V Serial TDM data input Schmitt trigger input, VIL=1.0V, VIH=2.0V Serial TDM data output Schmitt output, VOH=0.9*DVDD, VOL=0.1*DVDD Schmitt input (VIL=1.45V, VIH=1.85V)/TTL output S/PDIF Input/Signal to power down external amp S/PDIF Output General Purpose Input/Output 0 General Purpose Input/Output 1 General Purpose Input/Output 2 General Purpose Input/Output 3 TTL output has 12 mA@75 driving capability. Schmitt input/output, VIL=1.45V, VIH=1.85V Schmitt input/output, VIL=1.45V, VIH=1.85V Schmitt input/output, VIL=1.45V, VIH=1.85V Schmitt input/output, VIL=1.45V, VIH=1.85V Total: 11 Pins
Name RESET# SYNC BITCLK SDATA-OUT SDATA-IN SPDIFI / EAPD SPDIFO GPIO0 GPIO1 GPIO2 GPIO3
6.2.
Name PCBEEP LINE2-L LINE2-R MIC2-L MIC2-R CD-L CD-G CD-R MIC1-L MIC1-R LINE1-L LINE1-R
Analog I/O Pins
Type I IO IO IO IO I I I IO IO IO IO Pin # 12 14 15 16 17 18 19 20 21 22 23 24 Table 2. Analog I/O Pins Description Characteristic Definition External PCBEEP input Analog input. 1.6Vrms of full scale input nd 2 line input left channel Analog input/output. Default is input (JACK-E) 2nd line input right channel Analog input/output. Default is input (JACK -E) 2nd stereo microphone input Analog input/output. Default is input (JACK -F) left channel 2nd stereo microphone input Analog input/output. Default is input (JACK -F) right channel CD input left channel Analog input. 1.6Vrms of full scale input CD input reference ground Analog input. 1.6Vrms of full scale input CD input right channel Analog input. 1.6Vrms of full scale input 1st stereo microphone input Analog input/output. Default is input (JACK -B) left channel 1st stereo microphone input Analog input/output. Default is input (JACK -B) right channel 1st line input left channel Analog input/output. Default is input (JACK -C) 1st line input right channel Analog input/output. Default is input (JACK -C) 6 Track ID: JATR-1076-21 Rev. 1.3
2 Channel High Definition Audio Codec
ALC260(D) Datasheet
Name
LINE-OUT-L LINE-OUT-R
HP-OUT-L HP-OUT-R
MONO-OUT
Sense A Sense B DCVOL
Type IO IO IO IO O I I I
Pin # 35 36 39 41 37 13 34 33
Description Secondary out left channel Secondary out right channel First out left channel First out right channel MONO output Jack Detect pin l Jack Detect pin 2 DC sense for volume control
Characteristic Definition Analog output (JACK -D) Analog output (JACK -D) Analog output (JACK -A) Analog output (JACK -A) Analog mono output is summation of (L+R)/2. Analog DC input from 0V~5.0V Analog DC input from 0V~5.0V Analog DC input from 0V~5.0V Total: 20 Pins
6.3.
Name VREF
Filter/Reference
Type O O O O O I Pin # 27 28 29 30 31 32 40 Table 3. Filter/Reference Description Characteristic Definition 2.5V Reference voltage 1uf capacitor to analog ground Bias voltage for MIC1 jack 2.5V/3.75Vreference voltage 2.5V/3.75Vreference voltage Bias voltage for LINE1 jack Bias voltage for MIC2 jack 2.5V/3.75Vreference voltage 2.5V/3.75Vreference voltage Bias voltage for LINE2 jack Bias voltage for MIC1 jack 2.5V/3.75Vreference voltage 20K, 1% ohm resistor to analog ground Jack detect reference resistor Total: 7 Pins
MIC1-VREFO-L
LINE1-VREFO MIC2-VREFO LINE2-VREFO
MIC1-VREFO-R JDREF
6.4.
Name AVDD1 AVSS1 AVDD2 AVSS2 DVDD1 DVSS1 DVDD2 DVSS2
Power/Ground
Type I I I I I I I I Pin # 25 26 38 42 1 4 9 7 Table 4. Power/Ground Description Characteristic Definition Analog power for mixer and amplifier Analog VDD (5.0V or 3.3V) Analog GND Analog ground for mixer and amplifier Analog power for DACs and ADCs Analog VDD (5.0V or 3.3V) Analog GND Analog ground for DACs and ADCs Digital VDD (3.3V) Digital power Digital GND Digital ground Digital VDD (3.3V) Digital power Digital GND Digital ground Total: 8 Pins
2 Channel High Definition Audio Codec
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ALC260(D) Datasheet
7.
7.1.
High Definition Audio Link Protocol
Link Signals
The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz BIT-CLK sent by the HDA controller. The input and output streams, including command and PCM data, are isochronous with a 48kHz frame rate. Figure 4 shows the basic concept of the HDA link protocol.
Previous Frame BCLK Frame SYNC= 8 BCLK SYNC
Tframe_sync = 20.833 s (48KHz)
Next Frame
Stream 'A' Tag (Here 'A' = 5)
Stream 'B' Tag (Here 'B' = 6)
SDO
Command Stream (40-bit data)
Stream 'A' Data
Stream 'B' Data
SDI
Response Stream (36-bit data)
Stream 'C' Tag
Stream 'C' Data (n bytes + 10-bit data)
RST#
Figure 4. HDA Link Protocol
2 Channel High Definition Audio Codec
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ALC260(D) Datasheet
7.1.1.
Item BCLK SYNC SDO
Signal Definitions
Table 5. Link Signal Definitions Description 24.0MHz bit-clock sourced from the HDA controller and connecting to all codecs. 48kHz signal is used to synchronize input and output streams on the link. It is sourced from the HDA controller and connects to all codecs. Serial data output signal driven by the HDA controller to all codecs. Commands and data streams are carried on SDO. The data rate is double pumped; the controller drives data onto the SDO, the codec samples data present on SDO with respect to each edge of BCLK. The HDA controller must support at least one SDO. To extend outbound bandwidth, multiple SDOs may be supported. Serial data input signal driven by the codec. This is point-to-point serial data from the codec to the HDA controller. The controller must support at least one SDI. Up to a maximum of 15 SDI's can be supported. SDI is driven by the codec at each rising edge of BCLK, and sampled by the controller at each rising edge of BCLK. SDI can be driven by the controller to initialize the codec's ID. Active low reset signal. Asserted to reset the codec to default power on state. RST# is sourced from the HDA controller and connects to all codecs.
SDI
RST#
Signal Name BCLK SYNC SDO SDI RST#
Source Controller Controller Controller Codec/Controller Controller
Table 6. HDA Signal Definitions Type for Controller Description Output Global 24.0MHz bit clock. Output Global 48kHz Frame Sync and outbound tag signal. Output Serial data output from controller. Input/Output Serial data input from codec. Weakly pulled down by the controller. Output Global active low reset signal.
BCLK SYNC
8-Bit Frame SYNC Start of Frame
SDO SDI
7
6
5
4
3
2
1
0 999 998 997 996 995 994 993 992 991 990
3
2
1
0
499
498
497
496
495
494
Codec samples SDO at both rising and falling edge of BCLK Controller samples SDI at rising edge of BCLK
Figure 5. Bit Timing
2 Channel High Definition Audio Codec
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ALC260(D) Datasheet
7.1.2.
Signaling Topology
The HDA controller supports two SDOs for the outbound stream, up to 15 SDIs for the inbound stream. RST#, BCLK, SYNC, SDO0 and SDO1 are driven by the controller to codecs. Each codec drives its own point-to-point SDI signal(s) to the controller. Figure 6 shows the possible connections between the HDA controller and codecs: 1. 2. 3. 4. Codec 0 is a basic connection. There is one single SDO and one single SDI for normal transmission Codec 1 has two SDOs for doubled outbound rate, a single SDI for normal inbound rate Codec 3 supports a single SDO for normal outbound rate, and two SDIs for doubled inbound rate Codec N has two SDOs and multiple SDIs
The multiple SDOs and multiple SDIs are used to expand the transmission rate between controller and codecs. The following section `Frame Composition', describes the detailed outbound and inbound stream compositions for single and multiple SDOs/SDIs. The connections shown in Figure 6 can be implemented concurrently in an HDA system. The ALC260(D) is designed to receive a single SDO stream.
SDI14 . . . SDI13 SDI2 HDA SDI1 Controller SDI0 SDO1 SDO0 SYNC BCLK RST#
. . .
2 Channel High Definition Audio Codec
SDO0 SYNC BCLK RST#
S DI0 SDO1 SDO0 SYNC BCLK RST#
SDI2 SDI1 SDI0 SDO1 SDO0 SYNC BCLK RST#
SDO0 SYNC BCLK RST#
SDI0
SDI1 SDI0
...
Codec 0 Single SDO Single SDI
Codec 1 Two SDOs Single SDI
Codec 2 Single SDO Two SDIs
Codec N Two SDOs Multiple SDIs
Figure 6. Signaling Topology
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ALC260(D) Datasheet
7.2.
7.2.1.
Frame Composition
Outbound Frame - Single SDO
An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one or multiple sample blocks in a data stream. Only one sample block exists in a stream if the HDA controller delivers a 48kHz rate of samples to the codec. Multiple sample blocks in a stream means the sample rate is a multiple of 48kHz. This means there should be 2 blocks in the same stream to carry 96kHz samples (Figure 7). For outbound frames, the stream tag is not in SDO, but in the SYNC signal. A new data stream is started at the end of the stream tag. The stream tag includes a 4-bit preamble and 4-bit stream ID (Figure 8). To keep the cadence of converters bound to the same stream, samples for these converters must be placed in the same block.
Previous Frame
A 48kHz Frame is composed of Command stream and multiple Data streams Stream 'A' Tag (Here 'A' = 5) Stream 'X' Tag (Here 'X' = 6)
Next Frame
Frame SYNC
SYNC
SDO
Command Stream
Stream 'A' Data
Stream 'X' Data
0s
Sample Block(s) Block 1 Block 2 Sample 2 ... lsb .. . .. .
One or multiple blocks in a stream
Null Field
Padded at the end of Frame
Block Y
For 48kHz rate, only Block1 is included For 96kHz rate, Block1 includes (N)th time of samples, Block2 includes (N+1)th time of samples
Sample 1
Sample Z Z channels of PCM Sample
msb
msb first in a sample
Figure 7. SDO Outbound Frame
BCLK
Stream Tag
msb SYNC
Preamble (4-Bit)
lsb
1010
Stream=10 (4-Bit) ms b Data of Stream 10
SDO
76543210 Previous Stream
Figure 8. SDO Stream Tag is Indicated in SYNC 2 Channel High Definition Audio Codec 11 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
7.2.2.
Inbound Frame - Single SDI
An Inbound Frame - Single SDI is composed of one 36-bit response stream and multiple data streams. Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at each rising edge of BCLK. The controller also samples data at the rising edge of BCLK (Figure 9). The SDI stream tag is not carried by SYNC, but included in the SDI. A complete SDI data stream includes one 4-bit stream tag, one 6-bit data length, and n-bit sample blocks. Zeros will be padded if the total length of the contiguous sample blocks within a given stream is not of integral byte length (Figure 10).
Previous Frame A 48kHz Frame is Composed of a Response Stream and Multiple Data streams Next Frame
Frame SYNC SYNC
SDI
Response Stream
Stream 'A'
Stream 'X'
0s
Null Field Stream Tag Block 1 Sample Block(s) ... ... lsb Block Y Null Pad
Padded at the end of Frame
Block 2
For 48kHz rate, only Block1 is included For 96kHz rate, Block{1, 2} includes {(N)th (N+1)th} time of samples
Sample 1 Sample 2 msb ...
Sample Z Z channels of PCM Sample
msb first in a sample
Figure 9. SDI Inbound Stream
BCLK
Stream Tag Data Length in Bytes B6 B5 B4 B3 B2 B1
n-Bit Sample Block
Null Pad 0 0 0 0
Next Stream
SDI
B9
B8
B7
B0 Dn-1 Dn-2
D0
(Data Length in Bytes *8)-Bit A Complete Stream
Figure 10. SDI Stream Tag and Data
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ALC260(D) Datasheet
7.2.3.
Variable Sample Rates
The HDA link is designed for sample rates of 48kHz. Variable sample rates are delivered in multiple or sub-multiple rates of 48kHz. Two sample blocks per frame result in a 96kHz delivery rate. One sample block over two frames results in a 24kHz delivery rate. The HDA specification states that the sample rate of the outbound stream be synchronized by the controller, not by the codec. Each stream has its own sample rate, independent of any other stream. The HDA controller supports 48kHz and 44.1kHz base rates. Table 7 shows the recommended sample rates based on multiples or sub-multiples of one of the two base rates. Rates in sub-multiples (1/n) of 48kHz are interleaving n frames containing no sample blocks. Rates in multiples (n) of 48kHz contain n sample blocks in a frame. Table 8 shows the delivery cadence of variable rates based on 48kHz. The HDA link is defined to operate at a fixed 48kHz frame rate. To deliver samples in (sub) multiple rates of 44.1kHz, an appropriate ratio between 44.1kHz and 48kHz must be maintained to avoid frequency drift. The appropriate ratio between 44.1kHz and 48kHz is 147/160. Meaning 147 sample blocks are transmitted every 160 frames. The cadence `12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)', interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence AND interleave n empty frames. Rates in multiples (n) of 44.1kHz applying this cadence contain n sample blocks in the non-empty frame AND interleave an empty frame between non-empty frames (Table 9, page 14).
(Sub) Multiple 1/6 1/4 1/3 1/2 2/3 1 2 4 Table 7. Defined Sample Rate and Transmission Rate 48kHz Base 44.1kHz Base 8kHz (1 sample block every 6 frames) 12kHz (1 sample block every 4 frames) 11.025kHz (1 sample block every 4 frames) 16kHz (1 sample block every 3 frames) 24kHz (1 sample block every 2 frames) 22.05kHz (1 sample block every 2 frames) 32kHz (2 sample blocks every 3 frames) 48kHz (1 sample block per frame) 44.1kHz (1 sample block per frame) 96kHz (2 sample blocks per frame) 88.2kHz (2 sample blocks per frame) 192kHz (4 sample blocks per frame) 176.4kHz (4 sample blocks per frame)
Table 8. 48kHz Variable Rate of Delivery Timing Rate Delivery Cadence Description 8kHz YNNNNN (repeat) One sample block is transmitted every 6 frames 12kHz YNNN (repeat) One sample block is transmitted every 4 frames 16kHz YNN (repeat) One sample block is transmitted every 3 frames 32kHz Y2NN (repeat) One sample block is transmitted every 6 frames 48kHz Y (repeat) One sample block is transmitted every 6 frames 96kHz Y2 (repeat) Two sample blocks are transmitted in each frame 192kHz Y4 (repeat) Four sample blocks are transmitted in each frame N: No sample block in a frame Y: One sample block in a frame Yx: X sample blocks in a frame
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ALC260(D) Datasheet
Table 9. 44.1kHz Variable Rate of Delivery Timing Rate Delivery Cadence 11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat) 88.2kHz 122-112-112-122-112-112-122-112-112-122-112-112-112- (repeat) 174.4kHz 124-114-114-124-114-114-124-114-114-124-114-114-114- (repeat)
11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN {11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN {-} =NNNN 22.05kHz: {12}=YNYNYNYNYNYNYNYNYNYNYNYN {11}=YNYNYNYNYNYNYNYNYNYNYN {-} =NN 44.1kHz: 88.2kHz: 174.4kHz: 12- =Contiguous 12 frames containing 1 sample blocks each, followed by one frame with no sample block. 122- =Contiguous 12 frames containing 2 sample blocks each, followed by one frame with no sample block. 124- =Contiguous 12 frames containing 4 sample blocks each, followed by one frame with no sample block.
7.3.
* *
Reset and Initialization
There are two types of reset within an HDA link: Link Reset: Generated by assertion of the RST# signal; all codecs return to their power-on state Codec Reset: Generated by software; directs a command to reset a specific codec back to its default state Link Reset Codec Reset Codec changes its power state (e.g., hot docking a codec to an HDA system)
An initialization sequence is requested after any of the following three events: 1. 2. 3.
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ALC260(D) Datasheet
7.3.1.
1. 2. 3.
Link Reset
A link reset may be caused by 3 events: The HDA controller asserts RST# for any reason (power up, or PCI reset) Software initiates a link reset via the `CRST' bit in the Global Control Register (GCR) of the HDA controller Software initiates power management sequences. Figure 11, page 15, shows the `Link Reset' timing including the `Enter' sequence ( ~ ) and `Exit' sequence ( ~ )
Enter `Link Reset': Software writes a 0 to the `CRST' bit in the Global Control Register of the HDA controller to initiate a link reset As the controller completes the current frame, it does not signal the normal 8-bit frame SYNC at the end of the frame The controller drives SYNC and all SDOs to low. Codecs also drive SDIs to low The controller asserts the RST# signal to low, and enters the `Link Reset' state All link signals driven by controller and codecs should be tri-state by internal pull low resistors Exit from `Link Reset': BCLK is re-started for any reason (codec wake-up event, power management, etc.) Software is responsible for de-asserting RST# after a minimum of 100sec BCLK running time (the 100sec provides time for the codec PLL to stabilize) Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC When the codec drives it's SDI to request an initialization sequence (when the SDI is driven high at the last bit of frame SYNC), it means the codec requests an initialization sequence)
Previous Frame 4 BCLK 4 BCLK Link in Reset >=100 usec >= 4 BCLK Initialization Sequence
BCLK SYNC
2 Normal Frame SYNC is absent Driven Low Normal Frame SYNC 8 Driven Low Pulled Low Wake Event 9
Pulled Low
SDOs SDIs RST#
1 3
Driven Low
Pulled Low
Pulled Low 4 5 6 7
Figure 11. Link Reset Timing 2 Channel High Definition Audio Codec 15 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
7.3.2.
Codec Reset
A `Codec Reset' is initiated via the Codec RESET command verb. It results in the target codec being reset to the default state. After the target codec completes its reset operation, an initialization sequence is requested.
7.3.3.
Codec Initialization Sequence
The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the controller The codec will stop driving the SDI in this turnaround period The controller drives the SDI to assign a CAD to the codec The controller releases SDI after the CAD has been assigned Normal operation state
Exit from Reset Connection Frame Turnaround Frame (Non-48kHz Frame) Address Frame (Non-48kHz Frame) Normal Operation
BCLK SYNC SDIx RST#
1 2 3
Frame SYNC
Frame SYNC
4 5 6 SD14 7 8
Frame SYNC Response
SD0 SD1
Codec Drives SDIx
Codec Turnaround (477 BCLK Max.)
Controller Drives SDIx
Controller Turnaround (477 BCLK Max.)
Codec Drives SDIx
Figure 12. Codec Initialization Sequence
2 Channel High Definition Audio Codec
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ALC260(D) Datasheet
7.4.
7.4.1.
Verb and Response Format
Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with 12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the 4-bit verb structure of a command stream sent from the controller to operate the codec. Table 11 is the 12-bit verb structure that gets and controls parameters in the codec.
Bit [39:32] Reserved Table 10. 40-Bit Commands in 4-Bit Verb Format Bit [31:28] Bit [27:20] Bit [19:16] Codec Address Node ID Verb ID Table 11. 40-Bit Commands in 12-Bit Verb Format Bit [31:28] Bit [27:20] Bit [19:8] Codec Address Node ID Verb ID Bit [15:0] Payload
Bit [39:32] Reserved
Bit [7:0] Payload
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the codec in response to a current command verb. The codec will send Solicited Response data in the next frame, without regard to the Set (Write) or Get (Read) command. The 32-bit Response is interpreted by software, opaque to the controller. Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI status information can be actively delivered to the controller and interpreted by software. The `Tag' in Bit [31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Bit [35] Valid Table 12. Solicited Response Format Bit [34] Bit [33:32] Unsol=0 Reserved Bit [31:0] Response
Table 13. Unsolicited Response Format Bit [35] Bit [34] Bit [33:32] Bit [31:26] Bit [27:0] Valid Unsol=1 Reserved Tag[5:0] Response Note: The response stream in the link protocol is 36-bits wide. The response is placed in the lower 32-bit field. Bit-35 is a `Valid' bit to indicate the response is `Ready'. Bit-34 is set to indicate that an unsolicited response was sent.
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ALC260(D) Datasheet
7.5.
Power Management
The ALC260(D) does not support Wake-Up events when in low-power mode. All power management state changes in widgets are driven by software. Table 14 shows the System Power State Definitions. In the ALC260(D), only the audio function (NID=01h) supports power control. Software may have various power states depending on system configuration. Table 15 indicates those nodes that support power management. To simplify power control, software can configure whole codec power states through the audio function (NID=01h). Output converters (DACs) and input converters (ADCs) have no individual power control.
Power States D0 D1 D2 D3 (Hot) D3 (Cold) Table 14. System Power State Definitions Definitions All power on. Individual DACs and ADCs can be powered up or down as required. All amplifiers and converters (DACs and ADCs) are powered down. State maintained; analog reference stays up. All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but analog reference off (D1 + analog reference off). Power still supplied. The codec stops the internal clock. State is maintained. All power removed. State lost.
Table 15. Power Controls in NID is 01h, 02h~05h, 07h~09h Description D0 D1 D2 LINK Response Normal Normal Normal DAC Normal PD PD MIC ADC Normal PD PD MIX ADC Normal PD PD All Headphone Drivers Normal Normal PD All Mixers Normal Normal PD All Reference Normal Normal PD Note: PD=Powered Down Item Audio Function (NID=01h)
D3 PD PD PD PD PD PD PD
Link Reset PD PD PD PD Normal Normal Normal
Condition LINK Response powered down
MIC ADC powered down LINE ADC powered down MIX ADC powered down Headphone Driver powered down Mixers powered down Reference power down
Table 16. Powered Down Conditions Description Internal clock is stopped. SDATA-IN and S/PDIF-OUT are floated with pulled low 47K resistors internally. S/PDIF-IN is also floated. Detection of `Link Reset Entry' and `Link Reset Exit' sequences are supported. All states are maintained if DVDD is supplied. Analog block and digital filter are powered down. The data on SDATA-IN is quiet. Analog block and digital filter are powered down. Analog block and digital filter are powered down. The data on SDATA-IN is quiet. All headphone drivers are powered down. All internal mixer widgets are powered down. The DC reference and VREFOUTx at individual pin complexes are still alive. All internal references, DC reference, and VREFOUTx at individual pin complexes are off. 18 Track ID: JATR-1076-21 Rev. 1.3
2 Channel High Definition Audio Codec
ALC260(D) Datasheet
8.
Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC260(D). If a verb is not supported by the addressed widget, it will respond with 32 bits of `0'. Refer to Figure 1, page 4, to get the NID (Node ID) assigned for each widget.
8.1.
Verb - Get Parameters (Verb ID=F00h)
The `Get Parameters' verb is used to get system information and the function capabilities of the HDA codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget; some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format, page 17, to get detailed information about supported parameters.
Table 17. Verb - Get Parameters (Verb ID=F00h) Get Parameter Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=00h Verb ID=F00h Parameter ID[7:0] 32-bit Response Note: If the parameter ID is not supported, the returned response is 32 bits of `0'.
8.1.1.
Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 18. Parameter - Vendor ID (Verb ID=F00h, Parameter ID=00h) Codec Response Format Bit Description 31:16 Vendor ID=10ECh (Realtek's PCI vendor ID). 15:0 Device ID=0260h.
8.1.2.
Parameter - Subsystem ID (Verb ID=F00h, Parameter ID=01h)
Table 19. Parameter - Subsystem ID (Verb ID=F00h, Parameter ID=01h) Codec Response Format Bit Description 31:16 The SubSystem ID is used to identify the function group. SubSystem ID=0260h for the ALC260 and the ALC260-LF. SubSystem ID=0000h for other versions. 15:8 Reserved. 7:0 Assembly ID.
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ALC260(D) Datasheet
8.1.3.
Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 20. Parameter - Revision ID (Verb ID=F00h, Parameter ID=02h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's. 23:20 MajRev. The major version number (in decimal) of the HDA Specification. 19:16 MinRev. The minor version number (in decimal) of the HDA Specification. 15:8 Revision ID. The vendor's revision number. 00h is for the first silicon version, 01h is for the second version, etc. 7:0 Stepping ID. The vendor's stepping number within the given Revision ID.
8.1.4.
Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes associated with the root node. For function group nodes, it provides the total number of widgets associated with this function node.
Table 21. Parameter - Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's. 23:16 Starting Node Number. The starting node number in the sequential widgets. 15:8 Reserved. Read as 0's. 7:0 Total Number of Nodes. For a root node, the total number of function groups in the root node. For a function group, the total number of widget nodes in the function group.
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ALC260(D) Datasheet
8.1.5.
Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h)
Table 22. Parameter - Function Group Type (Verb ID=F00h, Parameter ID=05h) Codec Response Format Bit Description 31:9 Reserved. Read as 0's. 8 UnSol Capable. 0: Unsolicited response is not supported by this function group 1: Unsolicited response is supported by this function group 7:0 Function Group Type. 00h: Reserved 01h: Audio Function 02h: Modem Function 03h~7Fh: Reserved 80h~FFh: Vendor Defined Function
8.1.6.
Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Table 23. Parameter - Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) Codec Response Format Bit Description 31:17 Reserved. Read as 0's. 16 Beep Generator. A `1' indicates the presence of an integrated Beep generator within the Audio Function Group. 15:12 Reserved. Read as 0's. 11:8 Input Delay. 7:4 Reserved. Read as 0's. 3:0 Output Delay.
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ALC260(D) Datasheet
8.1.7.
Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Table 24. Parameter - Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) Codec Response Format Bit Description 31:24 Reserved. Read as 0's. 23:20 Widget Type. 0h: Audio Output 1h: Audio Input 2h: Mixer 3h: Selector 4h: Pin Complex 5h: Power Widget 6h: Volume Knob Widget 7h~Eh: Reserved Fh: Vendor defined audio widget 19:16 Delay. Samples delayed between the HDA link and widgets. 15:11 Reserved. Read as 0's. 10 Power Control. 0: Power state control is not supported on this widget 1: Power state is supported on this widget 9 Digital. 0: An analog input or output converter 1: A widget translating digital data between the HDA link and digital I/O (S/PDIF, I2S, etc.) 8 ConnList. Connection List. 0: Connected to HDA link. No Connection List Entry should be queried 1: Connection List Entry must be queried DACs are directly connected to the HDA link. No connection list entry need be queried for DACs. 7 UnsolCap. Unsolicited Capable. 0: Unsolicited response is not supported 1: Unsolicited response is supported The S/PDIF-IN converter, Pin Complexes, and DCVOL will generate unsolicited responses. 6 ProcWidget. Processing Widget. 0: No processing control 1: Processing control is supported Only a Realtek defined widget has processing control. 5 Reserved. Read as 0. 4 Format Override. Different rates are supported for output converters. The supported format (parameter ID=0Ah) must be queried. 3 AmpParOvr. AMP Param Override. Supports amplifiers (Gain Control) in individual output Pin Complexes, ADCs, and Mixer widgets 2 OutAmpPre. Out AMP Present. Supports amplifiers (Gain Control) in individual output pin complexes. 1 InAmpPre. In AMP Present. Supports amplifiers (Gain Control) in individual ADCs and Mixer widgets. 0 Stereo. 0: Mono Widget 1: Stereo Widget
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ALC260(D) Datasheet
8.1.8.
Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Provides default information about formats. Individual converters have their own parameters to provide supported formats if their `Format Override' bit is set.
Table 25. Parameter - Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) Codec Response Format Bit Description 31:21 Reserved. Read as 0's. 20 B32. 32-bit audio format support. 0: Not supported 1: Supported 19 B24. 24-bit audio format support. 0: Not supported 1: Supported All DACs and S/PDIF-IN/OUT support 24-bit format. 18 B20. 20-bit audio format support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 20-bit format. 17 B16. 16-bit audio format support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 16-bit format. 16 B8. 8-bit audio format support. 0: Not supported 1: Supported 15:12 Reserved. Read as 0's. 11 R12. 384kHz (=8*48kHz) rate support. 0: Not supported 1: Supported 10 R11. 192kHz (=4*48kHz) rate support. 0: Not supported 1: Supported DAC and S/PDIF-OUT converter supports 192kHz rate. 9 R10. 176.4Hz (=4*44.1kHz) rate support. 0: Not supported 1: Supported 8 R9. 96kHz (=2*48kHz) rate support. 0: Not supported 1: Supported All DACs except Surr-Back DAC, ADCs, and S/PDIF-IN/OUT support 96kHz rate. 7 R8. 88.2kHz (=2*44.1kHz) rate support. 0: Not supported 1: Supported
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ALC260(D) Datasheet
Codec Response Format Bit Description 6 R7. 48kHz rate support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 48kHz rate. 5 R6. 44.1kHz rate support. 0: Not supported 1: Supported All DACs, ADCs, and S/PDIF-IN/OUT support 48kHz rate. 4 R5. 32kHz (=2/3*48kHz) rate support. 0: Not supported 1: Supported 3 R4. 22.05kHz (=1/2*44.1kHz) rate support. 0: Not supported 1: Supported 2 R3. 16kHz (=1/3*48kHz) rate support. 0: Not supported 1: Supported 1 R2. 11.025kHz (=1/4*44.1kHz) rate support. 0: Not supported 1: Supported 0 R1. 8kHz (=1/6*48kHz) rate support. 0: Not supported 1: Supported
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ALC260(D) Datasheet
8.1.9.
Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters have their own parameters to provide supported formats if the `Format Override' bit is set.
Table 26. Parameter - Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Codec Response Format Bit Description 31:3 Reserved. Read as 0's. 2 AC3. 0: Not supported 1: Supported 1 Float32. 0: Not supported 1: Supported 0 PCM. 0: Not supported 1: Supported
8.1.10. Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 27. Parameter - Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) Codec Response Format Bit Description 31:16 Reserved. Read as 0's. 15:8 VREF Control Capability. `1' in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of AVDD. 7:6 5 4 3 2 1 0 Reserved 100% 80% Reserved Ground 50% Hi-Z 7 L-R Swap. Indicates the capability of swapping the left and rights. Not supported. This bit is read as 0. 6 Balanced I/O Pin. `1' indicates this pin complex has balanced pins. 5 Input Capable. `1' indicates this pin complex supports input. 4 Output Capable. `1' indicates this pin complex supports output. 3 Headphone Drive Capable. `1' indicates this pin complex has an amplifier to drive a headphone.
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ALC260(D) Datasheet
Codec Response Format Bit Description 2 Presence Detect Capable. `1' indicates this pin complex can detect whether there is anything plugged in. Uses dedicated Jack-Detect pins to detect when a jack is plugged in. 1 Trigger Required. `1' indicates whether a software trigger is required for an impedance measurement. 0 Impedance Sense Capable. `1' indicates this pin complex can perform analog sensing on the attached device to determine its type.
8.1.11. Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the `AMP Param Override' bit is set.
Table 28. Parameter - Amplifier Capabilities (Verb ID=F00h, Input Amp Parameter ID=0Dh) Codec Response Format Bit Description 31 (Input) Mute Capable. 30:23 Reserved. Read as 0. 22:16 Step Size. Indicates the size of each step in the gain range. Permanently set to `3' (indicates a step of 1dB). 15 Reserved. Read as 0. 14:8 Number of Steps. Indicates the number of steps in the gain range. `0' means the gain is fixed. 7 Reserved. Read as 0. 6:0 Offset. Indicates which step is 0dB.
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ALC260(D) Datasheet
8.1.12. Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the `AMP Param Override' bit is set.
Table 29. Parameter - Amplifier Capabilities (Verb ID=F00h, Output Amp Parameter ID=12h) Codec Response Format Bit Description 31 (Output) Mute Capable. 30:23 Reserved. Read as 0. 22:16 Step Size. Indicates the size of each step in the gain range. Permanently set to `3' (indicates a step of 1dB). 15 Reserved. Read as 0. 14:8 Number of Steps. Indicates the number of steps in the gain range. `0' means the gain is fixed. 7 Reserved. Read as 0. 6:0 Offset. Indicates which step is 0dB.
8.1.13. Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 30. Parameter - Connect List Length (Verb ID=F00h, Parameter ID=0Eh) Codec Response Format Bit Description 31:8 Reserved. Read as 0. 7 Short Form. 0: Short Form 1: Long Form 6:0 Connect List Length. Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one input, and there is no Connection Select Control (Not a MUX widget).
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ALC260(D) Datasheet
8.1.14. Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Table 31. Parameter - Supported Power States (Verb ID=F00h, Parameter ID=0Fh) Codec Response Format Bit Description 31:4 Reserved. Read as 0's. 3 D3Sup. 1: Power state D3 is supported. 2 D2Sup. 1: Power state D2 is supported. 1 D1Sup. 1: Power state D1 is supported. 0 D0Sup. 1: Power state D0 is supported.
8.1.15. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Table 32. Parameter - Processing Capabilities (Verb ID=F00h, Parameter ID=10h) Codec Response Format Bit Description 31:16 Reserved. Read as 0's. 15:8 NumCoeff. Number of Coefficient. 7:1 Reserved. Read as 0's. 0 Benign. 0: Processing unit is not linear and not time invariant 1: Processing unit is linear and is time invariant
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ALC260(D) Datasheet
8.1.16. Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Table 33. Parameter - GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Codec Response Format Bit Description 31 GPIWake=0. GPIO wake up function not supported. 30 GPIUnsol=1. GPIO unsolicited response not supported. 29:24 Reserved. Read as 0's. 23:16 NumGPIs=00h. No GPI pin is supported. 15:8 NumGPOs=00h. No GPO pin is supported. 7:0 NumGPIOs=04h for LQFP-48. A total of 4 GPIO pins are supported.
8.1.17. Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Table 34. Parameter - Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h) Codec Response Format for NID=1Bh (Volume Control Knob) Bit Description 31:8 Reserved. Read as 0's. 7 Delta. 0: Software cannot modify the Volume Control Knob volume 1: Software can write a base volume to the Volume Control Knob 6:0 NumSteps. The number of steps in the range of the Volume Control Knob.
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ALC260(D) Datasheet
8.2.
Verb - Get Connection Select Control (Verb ID=F01h)
Table 35. Verb - Get Connection Select Control (Verb ID=F01h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F01h 0's Bit[7:0] are Connection Index
Codec Response for NID=04h (MIC ADC) Bit Description 31:8 0's. 7:0 Connection Index currently Set (Default value is 00h). 00h: Pin complex - MIC1 01h: Pin complex - MIC2 02h: Pin complex - LINE1 03h: Pin complex - LINE2 04h: Pin complex - Analog CD-IN 05h: Pin complex - LINE-OUT 06h: Pin complex - HP-OUT Other: Reserved
Codec Response for NID=05h (LINE ADC) Bit Description 31:8 0's. 7:0 Connection Index currently Set (Default value is 02h). 00h: Pin complex - MIC1 01h: Pin complex - MIC2 02h: Pin complex - LINE1 03h: Pin complex - LINE2 04h: Pin complex - Analog CD-IN 05h: Sum Widget - Mixer 06h: Pin complex - LINE-OUT 07h: Pin complex - HP-OUT Other: Reserved
Codec Response for NID=0Bh (MIC1 Selector) Bit Description 31:8 0's. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved
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ALC260(D) Datasheet
Codec Response for NID=0Ch (MIC2 Selector) Bit Description 31:8 0's. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved
Codec Response for NID=0Dh (LINE1 Selector) Bit Description 31:8 0's. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved
Codec Response for NID=0Eh (LINE2 Selector) Bit Description 31:8 0's. 7:0 Connection Index currently Set (Default value is 00h). 00h: LOUT1 Sum Widget (NID=08h) 01h: LOUT2 Sum Widget (NID=09h) Other: Reserved
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).
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ALC260(D) Datasheet
8.3.
Verb - Set Connection Select (Verb ID=701h)
Table 36. Verb - Set Connection Select (Verb ID=701h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=701h Select Index [7:0] 0's for all nodes Note: See section 8.2 Verb - Get Connection Select Control (Verb ID=F01h), page 30, for details on widgets that support connection selection.
8.4.
Verb - Get Connection List Entry (Verb ID=F02h)
Table 37. Verb - Get Connection List Entry (Verb ID=F02h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F02h Offset Index - N[7:0] 32-bit Response
Codec Response for NID=04h (MIC ADC) Bit Description 31:24 Connection List Entry (N+3). Return 15h (=27, Pin Complex - LINE2) for N=0~3. Return 00h for n>3. 23:16 Connection List Entry (N+2). Return 14h (Pin Complex - LINE1) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 13h (Pin Complex-MIC2) for N=0~3. Return 0Fh (Pin Complex-LINE-OUT) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 12h (Pin Complex-MIC1) for N=0~3. Return 16h (Pin Complex-CD) for N=4~7. Return 00h for N>7.
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ALC260(D) Datasheet
Codec Response for NID=05h (MIX ADC) Bit Description 31:24 Connection List Entry (N+3). Return 15h (=27, Pin Complex - LINE2) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. Return 00h for n>7. 23:16 Connection List Entry (N+2). Return 14h (Pin Complex - LINE1) for N=0~3. Return 0Fh (Pin Complex-LINE-OUT) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 13h (Pin Complex-MIC2) for N=0~3. Return 07h (Sum Widget-Mixer) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 12h (Pin Complex-MIC1) for N=0~3. Return 16h (Pin Complex-CD) for N=4~7. Return 00h for N>7.
Codec Response for NID=07h (Mixer) Bit Description 31:24 Connection List Entry (N+3). Return 15h (Pin Complex - LINE2) for N=0~3. Return 10h (Pin Complex-HP-OUT) for N=4~7. Return 00h for N>7. 23:16 Connection List Entry (N+2). Return 14h (Pin Complex - LINE1) for N=0~3. Return 0Fh (Pin Complex - LINE-OUT) for N=4~7. Return 00h for N>7. 15:8 Connection List Entry (N+1). Return 13h (Pin Complex - MIC2) for N=0~3. Return 17h (Pin Complex - PCBEEP) for N=4~7. Return 00h for N>7. 7:0 Connection List Entry (N). Return 12h (Pin Complex - MIC1) for N=0~3. Return 16h (Pin Complex - CD) for N=4~7. Return 00h for N>7.
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ALC260(D) Datasheet
Codec Response for NID=08h (LOUT1 Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 02h (DAC) for N=0~3. Return 00h for N>3.
Codec Response for NID=09h (LOUT2 Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 02h (DAC) for N=0~3. Return 00h for N>3.
Codec Response for NID=0Ah (MONO Sum) Bit Description 31:24 Connection List Entry (N). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 07h (Mixer) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 02h (DAC) for N=0~3. Return 00h for N>3.
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ALC260(D) Datasheet
Codec Response for NID=0Bh (MIC1 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=0Ch (MIC2 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=0Dh (LINE1 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h. 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=0Eh (LINE2 Sel) Bit Description 31:24 Connection List Entry (N+3). Return 00h.
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Codec Response for NID=0Eh (LINE2 Sel) Bit Description 23:16 Connection List Entry (N+2). Return 00h. 15:8 Connection List Entry (N+1). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=0Fh (Pin Widget: LINE-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 08h (LOUT1 Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=10h (Pin Widget: HP-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 09h (LOUT2 Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=11h (Pin Widget: MONO-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Ah (MONO Sum Widget) for N=0~3. Return 00h for N>3.
Codec Response for NID=12h (Pin Widget: MIC1) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Bh (MIC1 Select Widget) for N=0~3. Return 00h for N>3.
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ALC260(D) Datasheet
Codec Response for NID=13h (Pin Widget: MIC2) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Ch (MIC2 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=14h (Pin Widget: LINE1) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Dh (LINE1 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=15h (Pin Widget: LINE2) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 0Eh (LINE2 Select Widget) for N=0~3. Return 00h for N>3. Codec Response for NID=18h (Pin Widget: S/PDIF-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 03h (NID=03h, S/PDIF-OUT converter) for N=0~3. Return 00h for N>3. Codec Response for NID=18h (Pin Widget: S/PDIF-OUT) Bit Description 31:8 Connection List Entry (N+3), (N+2), and (N+1). Return 000000h. 7:0 Connection List Entry (N). Return 19h (NID=19h, S/PDIF-IN Pin Widget) for N=0~3. Return 00h for N>3. Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h). Note: Long Form list entry not supported. The Short Form bit of the Connection List Length parameter is always `0'.
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ALC260(D) Datasheet
8.5.
Verb - Get Coefficient Index (Verb ID=Dh)
Table 38. Verb - Get Coefficient Index (Verb ID=Dh) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=Dh 0's Bit [15:0] are Coefficient Index
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh
Codec Response for NID=20h (Realtek Defined Hidden Registers) Bit Description 31:16 Reserved. Read as 0's. 15:0 Coefficient Index. Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h).
8.6.
Verb - Set Coefficient Index (Verb ID=5h)
Table 39. Verb - Set Coefficient Index (Verb ID=5h) Bit [19:16] Verb ID=5h Payload Bit [15:0] Coefficient Index [15:0] Codec Response Format Response [31:0] 0's for all nodes
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for All NID Bit Description 31:0 0's.
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ALC260(D) Datasheet
8.7.
Verb - Get Processing Coefficient (Verb ID=Ch)
Table 40. Verb - Get Processing Coefficient (Verb ID=Ch) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:16] Payload Bit [15:0] Response [31:0] CAd=X Node ID=Xh Verb ID=Ch 0's Processing Coefficient [15:0] Codec Response for NID=20h (Realtek Defined Hidden Registers) Bit Description 31:16 Reserved. Read as 0's. 15:0 Processing Coefficient.
Codec Response for Other NID Bit Description 31:0 Not supported (returns 00000000h).
8.8.
Verb - Set Processing Coefficient (Verb ID=4h)
Table 41. Verb - Set Processing Coefficient (Verb ID=4h) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=4h Coefficient [15:0] 0's for all nodes
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh
Codec Response for All NID Bit Description 31:0 0's.
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ALC260(D) Datasheet
8.9.
Verb - Get Amplifier Gain (Verb ID=Bh)
Table 42. Verb - Get Amplifier Gain (Verb ID=Bh) Codec Response Format Response [31:0] Bit[7:0] are responsible for `Get'
This verb is used to get gain/attenuation settings from each widget.
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh
Bit [19:16] Verb ID=Bh
Payload Bit [15:0] `Get' payload [15:0]
`Get' Payload in Command Bit[15:0] Bit Description 15 Get Input/Output. 0: Input amplifier gain is requested 1: Output amplifier gain is requested 14 Reserved. Read as 0. 13 Get Left/Right. 0: Right amplifier gain is requested 1: Left amplifier gain is requested This bit should be ignored for output amplifier and MONO widget. 12:4 Reserved. Read as 0's. 3:0 Index[3:0] for Input Source. Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for NID=04h (MIC ADC) and 05h(MIX ADC) Bit Description 31:8 0's. 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute). The Index bits in `Get/Set Amplifier gain' verb for MIC ADC and MIX ADC should be ignored. 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~35) specifying the volume from 0B~+35dB in 1dB steps. Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute).
Codec Response for NID=07h (MIXER Sum Widget) Bit Description 31:8 0's. 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute 1: Mute (Default for all Index). Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Gain [6:0]. 7-bit step value (0~65) specifying the volume from -35dB~+30dB in 1dB steps. Bit-15 is 1 in `Get Amplifier Gain': Read as 0's (No Output Amplifier Mute).
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
Codec Response for NID=08h~0Ah (Sum Widget: LOUT1, LOUT2, MONO Sum) Bit Description 31:8 0's. 7 Bit-15 is 0 in `Get Amplifier Gain': Input Amplifier Mute, 0: Unmute, 1: Mute Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Mute). 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0 (No Input Amplifier Gain) Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Gain [6:0]. 7-bit step value (0~64) specifying the volume from -64dB~0dB in 1dB steps. The Index bits in `Get/Set Amplifier gain' for output amplifiers of LOUT1, LOUT2, and MONO Sum should be ignored.
Codec Response for NID=0Fh, 10h, 12h~15h (Pin Complex: LINE-OUT/HP-OUT/MIC1/MIC2/LINE1/LINE2) Bit Description 31:8 0's. 7 Bit-15 is 0 in `Get Amplifier Gain': Read as 0. Bit-15 is 1 in `Get Amplifier Gain': Output Amplifier Mute, 0: Unmute, 1: Mute (NID=0Fh~15h,Default=1) 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0s. Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain).
Codec Response for NID =11h (Pin Complex: MONO-OUT) Bit Description 31:8 0's. 7 `Get Amplifier Gain'. [15]=0: Read as 0. `Get Amplifier Gain'. [15]=1 & `Get Amplifier Gain'.[13]=0: Read as 0. `Get Amplifier Gain'. [15]=1 & `Get Amplifier Gain'.[13]=1: Output Amplifier Mute: 0: Unmute 1: Mute The Index bits in `Get/Set Amplifier gain' verb should be ignored. 6:0 Bit-15 is 0 in `Get Amplifier Gain': Read as 0s. Bit-15 is 1 in `Get Amplifier Gain': Read as 0 (No Output Amplifier Gain).
Codec Response to Other NID Bit Description 31:0 Not supported (returns 00000000h).
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.10. Verb - Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 43. Verb - Set Amplifier Gain (Verb ID=3h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=3h Payload Bit [7:0] `Set' payload [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Set' Payload in Command Bit[15:0] Bit Description 15 Set Output Amp. `1' indicates output amplifier gain will be set. 14 Set Input Amp. `1' indicates input amplifier gain will be set. 13 Set Left Amp. `1' indicates left amplifier gain will be set. 12 Set Right Amp `1' indicates right amplifier gain will be set. 11:8 Index Offset (for input amplifiers on Sum widgets and Selector Widgets). 5 bits index offset in connection list is used to select which input gain will be set on a Sum or a Selector widget. The index is ignored if the node is not a Sum or a Selector widget, or the `Set Input Amp' bit is not set. 7 Mute. 0: Unmute 1: Mute (-gain) 6:0 Gain [6:0]. A 7-bit step value specifying the amplifier gain.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.11. Verb - Get Converter Format (Verb ID=Ah)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 44. Verb - Get Converter Format (Verb ID=Ah) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=Ah 0's Bit[15:0] are converter format
Codec Response for NID=02h, 03h (Output Converters: DAC and S/PDIF-OUT) Codec Response for NID=04h~06h (Input Converters: MIC, MIX DAC and S/PDIF-IN) Bit Description 31:16 Reserved. Read as 0. 15 Stream Type (TYPE). 0: PCM 1: Non-PCM 14 Sample Base Rate (BASE). 0: 48kHz 1: 44.1kHz 13:11 Sample Base Rate Multiple (MULT). 000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved. 10:8 Sample Base Rate Divisor (DIV). Not supported. Always read as 000b. 7 Reserved. Read as 0. 6:4 Bits per Sample (BITS). 000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: reserved 3:0 Reserved. Read as 0s.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.12. Verb - Set Converter Format (Verb ID=2h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 45. Verb - Set Converter Format (Verb ID=2h) Codec Response Format Bit [19:16] Payload Bit [15:0] Response [31:0] Verb ID=2h Set format [15:0] 0's for all nodes
`Set' payload in command Bit [15:0] Bit Description 31:16 Reserved. Read as 0. 15 Stream Type (TYPE). 0: PCM 1: Non-PCM 14 Sample Base Rate (BASE). 0: 48kHz 1: 44.1kHz 13:11 Sample Base Rate Multiple (MULT). 000b: *1 001b: *2 010b: *3 011b: *4 100b~111b: Reserved. 10:8 Sample Base Rate Divisor (DIV). 000b: /1 001b: /2 010b: /3 011b: /4 100b: /5 101b: /6 110b: /7 111b: /8 7 Reserved. Read as 0. 6:4 Bits per Sample (BITS). 000b: 8 bits 001b: 16 bits 010b: 20 bits 011b: 24 bits 100b: 32 bits 101b~111b: Reserved 3:0 Number of Channels. Reserved. Read as 0.
8.13. Verb - Get Power State (Verb ID=F05h)
Table 46. Verb - Get Power State (Verb ID=F05h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=F05h Payload Bit [7:0] 0's Codec Response Format Response [31:0] Power State [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:6 Reserved. Read as 0's. 5:4 PS-Act. Actual Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes (NID=01h), PS-Act is always equal to PS-Set. 2 Channel High Definition Audio Codec 44 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
Codec Response for NID=01h (Audio Function Group) Bit Description 3:2 Reserved. Read as 0's. 1:0 PS-Set, Set Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Set controls the current power setting of the referenced node.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).
8.14. Verb - Set Power State (Verb ID=705h)
Table 47. Verb - Set Power State (Verb ID=705h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=705h Payload Bit [7:0] Power State [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Power State' in Command Bit [7:0] Bit Description 7:6 Reserved. Read as 0's. 5:4 PS-Act. Actual Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3 PS-Act indicates the actual power state of the referenced node. 3:2 Reserved. Read as 0's. 1:0 PS-Set, Set Power State [1:0]. 00: Power state is D0 01: Power state is D1 10: Power state is D2 11: Power state is D3
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.15. Verb - Get Converter Stream, Channel (Verb ID=F06h)
Table 48. Verb - Get Converter Stream, Channel (Verb ID=F06h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F06h 0's Stream & Channel [7:0]
Codec Response for NID=02h, 03h (Output Converters: DAC and S/PDIF-OUT) Codec Response for NID=04h~06h (Input Converters: MIC ADC, MIX DAC and S/PDIF-IN) Bit Description 31:8 Reserved. Read as 0's. 7:4 Stream [3:0]. The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 3:0 Channel [3:0]. The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).
8.16. Verb - Set Converter Stream, Channel (Verb ID=706h)
Table 49. Verb - Set Converter Stream, Channel (Verb ID=706h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=706h Stream & Channel [7:0] 0's for all nodes `Stream and Channel' in Command Bit [7:0] Bit Description 31:8 Reserved. Read as 0's. 7:4 Set Stream [3:0]. The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc. 3:0 Set Channel [3:0]. The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its left and right channel.
2 Channel High Definition Audio Codec
46
Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.17. Verb - Get Pin Widget Control (Verb ID=F07h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 50. Verb - Get Pin Widget Control (Verb ID=F07h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F07h 0's Pin Control [7:0]
Codec Response for NID=0Fh, 10h, 11h, 12h, 13h, 14h, 15h (Pin Complex: LINE-OUT, HP-OUT, MONO-OUT, MIC1, MIC2, LINE1, LINE2) Bit Description 31:1 Reserved. Read as 0's. 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for a I/O unit). 0: Disabled 1: Enabled 6 Out Enable (Output Buffet Enable, EN_OBUF for a I/O unit). 0: Disabled 1: Enabled 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit). 0: Disabled 1: Enabled 4: Reserved. 2:0 VrefEn (Vrefout Enable Control). 000b: Hi-Z 001b: 50% of AVDD 010b: Ground 0V (Not supported) 011b: Reserved 100b: 80% of AVDD 101b: 100% of AVDD (Not supported) 110b~111b: Reserved Not supported)
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.18. Verb - Set Pin Widget Control (Verb ID=707h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 51. Verb - Set Pin Widget Control (Verb ID=707h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=707h Pin Control [7:0] 0's for all nodes
`Pin Control' in command [7:0]: (Pin: LINE-OUT, HP-OUT, MONO-OUT, MIC1, MIC2, LINE1, LINE2) Bit Description 31:1 Reserved. Read as 0's. 7 H-Phn Enable (Headphone Amplifier Enable, EN_AMP for an I/O unit). 0: Disabled 1: Enabled 6 Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit). 0: Disabled 1: Enabled 5 In Enable (Input Buffer Enable, EN_IBUF for a I/O unit). 0: Disabled 1: Enabled 4: Reserved. 2:0 VrefEn (Vrefout Enable Control). 000b: Hi-Z 001b: 50% of AVDD 010b: Ground 0V (Not supported) 011b: Reserved (Not supported) 100b: 80% of AVDD 101b: 100% of AVDD (Not supported) 110b~111b: Reserved (Not supported)
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.19. Verb - Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an unsolicited response to inform software of a real-time event.
Table 52. Verb - Get Unsolicited Response Control (Verb ID=F08h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID= F08h 0's 32-bit Response
Codec Response for NID=06h (S/PDIF-IN), 0Fh, 10h, 12h~15h (Pin Complex), 1Bh (Volume Knob), NID=01h for GPIO Bit Description 31:8 Reserved. Read as 0's. 7 Unsolicited Response is Enabled. 0: Disabled 1: Enabled 6 Reserved. Read as 0's. 5:0 Assigned Tag for Unsolicited Response. The tag [5:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h).
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.20. Verb - Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 53. Verb - Set Unsolicited Response Control (Verb ID=708h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=708h EnableUnsol [7:0] 0's for all nodes
`EnableUnsol' in Command Bit[7:0] for NID=01h (GPIO), 06h (S/PDIF-IN), 0Fh, 10h, 12h~15h (Pin), 1Bh (Vol Knob) Bit Description 31:8 Reserved. Read as 0's. 7 Enable Unsolicited Response. 0: Disable 1: Enable 6 Reserved. Read as 0's. 5:0 Tag for Unsolicited Response. Tag [5:0] is defined by software to assign a 6-bit tag for nodes that are enabled to generate unsolicited responses. A node enabled to generate unsolicited responses must return the assigned tag in the top six bits of every unsolicited response. According to the returned tag, software can identify which node generated the unsolicited response.
8.21. Verb - Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 54. Verb - Get Pin Sense (Verb ID=F09h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID= F09h Payload Bit [7:0] 0's Codec Response Format Response [31:0] 32-bit Response
Codec Response for NID=0F, 10h, 12h~15h (Pin Complex), 18h (Pin S/PDIF-OUT) and 19h (Pin S/PDIF-IN) Bit Description 31 Presence Detect Status. 0: No device is attached to the pin 1: Device is attached to the pin 30:0 Measured Impedance. 0x7FFFFFFF or 0xFFFFFFFF: Valid sense is not available or busy.
Codec Response for other NID Bit Description 31:0 Not supported (returns 00000000h). 2 Channel High Definition Audio Codec 50 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.22. Verb - Execute Pin Sense (Verb ID=709h)
Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 55. Verb - Execute Pin Sense (Verb ID=709h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID= 709h Right Channel [0] 0's for all nodes
`Payload' in Command Bit [7:0] for NID=0Fh, 10h, 12h~15h Bit Description 7:1 Reserved. Read as 0's. 0 Right (Ring) Channel Select. 0: Sense Left channel (Tip) 1: Sense Right channel (Ring)
8.23. Verb - Get Configuration Default (Verb ID=F1Ch)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 56. Verb - Get Configuration Default (Verb ID=F1Ch) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F1Ch 0's 32-bit Response
Codec Response for NID=0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 18h and 19h Bit Description 31:0 32-bit configuration information for each pin widget.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.24. Verb - Set Configuration Default Bytes 0 ~ 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0 ~ 3)
The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and 1Eh~1Fh such as placement and expected default device.
Table 57. Verb - Set Configuration Default Bytes 0 ~ 3 (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0 ~ 3) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Label [7:0] 0's for all nodes Verb ID=71Ch, 71Dh, 71Eh, 71Fh Note: Supported by Pin Widget NID=14h~1Bh, 1Eh and 1Fh. Other widgets will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's.
8.25. Verb - Get BEEP Generator (Verb ID=F0Ah)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 58. Verb - Get BEEP Generator (Verb ID= F0Ah) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F1Bh 0's Divider [7:0]
`Response' for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:0 Frequency Divider, F[7:0]. The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID Bit Description 31:0 0's.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.26. Verb - Set BEEP Generator (Verb ID=70Ah)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 59. Verb - Set BEEP Generator (Verb ID= 70Ah) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=71Bh Divider [7:0] 0's for all nodes
`Divider' in Set Command Bit Description 31:8 Reserved. 7:0 Frequency Divider, F[7:0]. The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0]. The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID Bit Description 31:0 0's.
8.27. Verb - Get GPIO Data (Verb ID= F15h)
Table 60. Verb - Get GPIO Data (Verb ID= F15h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=F15h Payload Bit [7:0] 0's Codec Response Format Response [31:0] 32-bit Response
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] (not supported). 3:0 GPIO [3:0] Data. The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Codec Response for Other NID Bit Description 31:0 0's.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.28. Verb - Set GPIO Data (Verb ID= 715h)
Table 61. Verb - Set GPIO Data (Verb ID= 715h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Bit [19:8] Verb ID=715h Payload Bit [7:0] Data [7:0] Codec Response Format Response [31:0] 0's for all nodes
`Data' in Set command for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] (not supported). 3:0 GPIO [3:0] Output Data. The value written determines the value driven on a pin that is configured as an output pin.
Codec Response for All NID Bit Description 31:0 0's.
8.29. Verb - Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 62. Verb - Get GPIO Enable Mask (Verb ID= F16h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F16h 0's EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 Reserved. 3:0 GPIO [3:0] Enable mask. 0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Codec Response for Other NID Bit Description 31:0 0's.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.30. Verb - Set GPIO Enable Mask (Verb ID=716h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 63. Verb - Set GPIO Enable Mask (Verb ID=716h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=716h Enable Mask [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] Enable Mask (not supported). 3:0 GPIO [3:0] Enable mask. 0: The corresponding GPIO pin is disabled and is in Hi-Z state 1: The corresponding GPIO pin is enabled. It's behavior is determined by the GPIO direction control
Codec Response for All NID Bit Description 31:0 0's.
8.31. Verb - Get GPIO Direction (Verb ID=F17h)
Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 64. Verb - Get GPIO Direction (Verb ID=F17h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=F17h 0's Direction [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] Direction Control (not supported). 3:0 GPIO [3:0] Direction Control. 0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Codec Response for Other NID Bit Description 31:0 0's.
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.32. Verb - Set GPIO Direction (Verb ID=717h)
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Table 65. Verb - Set GPIO Direction (Verb ID=717h) Codec Response Format Bit [19:8] Payload Bit [7:0] Response [31:0] Verb ID=717h Direction [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] Direction Control (not supported). 3:0 GPIO [3:0] Direction Control. 0: The corresponding GPIO pin is configured as an input 1: The corresponding GPIO pin is configured as an output
Codec Response for Other NID Bit Description 31:0 0's.
8.33. Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Table 66. Verb - Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F19h 0's UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] Unsolicited Enable Mask (not supported). 3:0 GPIO [3:0] Unsolicited Enable mask. 0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Codec Response for Other NID Bit Description 31:0 0's.
2 Channel High Definition Audio Codec
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Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.34. Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Table 67. Verb - Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=719h UnsolEnable [7:0] 0's for all nodes
Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:4 GPIO [7:4] Unsolicited Enable Mask (not supported). 3:0 GPIO [3:0] Unsolicited Enable Mask. 0: Unsolicited response will not be sent on link 1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Codec Response for Other NID Bit Description 31:0 0's.
8.35. Verb - Function Reset (Verb ID=7FFh)
Table 68. Verb - Function Reset (Verb ID=7FFh) Command Format (NID=01H) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=7FFh 0's 0's
Codec Response Bit Description 31:0 Reserved. Read as 0's. Note: The Function Reset command causes all widgets to return to their power-on default state.
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ALC260(D) Datasheet
8.36. Verb - Get Digital Converter Control (Verb ID= F0Dh)
Table 69. Verb - Get Digital Converter Control (Verb ID= F0Dh) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F0Dh 0's Bit[31:16]=0's, Bit[15:0] are SIC bits
NID=03h (S/PDIF-OUT) Response to `Get verb' - F0Dh (Control for SIC bit[15:0]) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 31:16 Read as 0's. 15 Reserved. Read as 0's. 14:8 CC[6:0] (Category Code). 7 LEVEL (Generation Level). 6 PRO (Professional or Consumer format). 0: Consumer format 1: Professional format Only consumer channel status format is supported. This bit is always 0. 5 /AUDIO (Non-Audio Data type). 0: PCM data 1: AC3 or other digital non-audio data 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 0 Digital Enable. DigEn. 0: OFF (S/PDIF-OUT is in Hi-Z) 1: ON NID=06h (S/PDIF-IN) Response to `Get verb (F0Dh)' Bit Description - S/PDIF-IN Channel Status 31:16 Reserved. Read as 0's. 15 Reserved. Read as 0's. 14:8 CC[6:0] (Category Code). 7 LEVEL (Generation Level). 6 PRO (Professional or Consumer format). 0: Consumer format 1: Professional format Only consumer channel status format is supported. This bit is always 0. 5 /AUDIO (Non-Audio Data type). 0: PCM data 1: AC3 or other digital non-audio data
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ALC260(D) Datasheet
NID=06h (S/PDIF-IN) Response to `Get verb (F0Dh)' Bit Description - S/PDIF-IN Channel Status 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 Reserved. 1 In`V'alid. V bit in sub-frame of S/PDIF-IN. 0: Data X and Y are valid, or S/PDIF-IN is not locked 1: At least one of data X and Y is invalid 0 DigEn (Digital Enable). 0: OFF 1: ON (S/PDIF-IN is enabled) Codec Response for Other NID Bit Description 31:0 0's.
8.37. Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Table 70. Verb - Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) Set Command Format (Verb ID=70Xh, Set Control 1) Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=70Dh SIC [7:0] 0's
Set Command Format (Verb ID=70Yh, Set Control 2) Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] CAd=X Node ID=Xh Verb ID=70Eh SIC [15:8]
Codec Response Format Response [31:0] 0's
`Payload' in Set Control 1 for NID=06h (S/PDIF-OUT) Bit Description - SIC (S/PDIF IEC Control) Bit [7:0] 7 LEVEL (Generation Level). 6 PRO (Professional or Consumer format). 0: Consumer format 1: Professional format 5 /AUDIO (Non-Audio Data type). 0: PCM data 1: AC3 or other digital non-audio data
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ALC260(D) Datasheet
`Payload' in Set Control 1 for NID=06h (S/PDIF-OUT) Bit Description - SIC (S/PDIF IEC Control) Bit [7:0] 4 COPY (Copyright). 0: Asserted 1: Not asserted 3 PRE (Pre-emphasis). 0: None 1: Filter pre-emphasis is 50/15 microseconds 2 VCFG for Validity Control (control V bit and data in Sub-Frame). 1 V for Validity Control (control V bit and data in Sub-Frame). 0 DigEn (Digital Enable). 0: OFF (S/PDIF-OUT is in Hi-Z) 1: ON
`Payload' in Set Control 2 for NID=06h (S/PDIF-OUT) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7 Reserved. Read as 0's. 6:0 CC[6:0] (Category Code).
`Payload' in Set Control 1 for NID=0Ah (S/PDIF-IN) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7:1 Reserved. 0 DigEn (Digital Enable). 0: OFF 1: ON (S/PDIF-IN is enabled)
`Payload' in Set Control 2 for NID=0Ah (S/PDIF-IN) Bit Description - SIC (S/PDIF IEC Control) Bit[7:0] 7:0 Reserved. Read as 0's. Note: Other widgets will ignore this verb.
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ALC260(D) Datasheet
8.38. Verb - Get/Set EAPD Enable (Verb ID= F0Ch/70Ch)
Table 71. Verb - Get/Set EAPD Enable (Verb ID= F0Ch/70Ch) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID= F0Ch 0's Bit[1] is EAPD Control
Codec response in Get Command for NID=0Fh (LINE-OUT Pin Widget), 10h (HP-OUT Pin Widget) Bit Description 31:4 Reserved. 2 L-R Swap. Not supported. Read as 0. 1 EAPD Enable. 0: EAPD pin state is not controlled by the power state of the corresponding pin widget 1: EAPD pin state is controlled by the power state of the corresponding pin widget 0 BTL Enable. Not supported. Read as 0.
Codec Response in Get Command for other NID Bit Description 31:0 0's.
Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh
Bit [19:8] Verb ID=70Ch
Payload Bit [7:0] Bit [1] is EAPD Control
Codec Response Format Response [31:0] 0's
Payload in Set Command for NID=0Fh (LINE-OUT Pin Widget), 10h (HP-OUT Pin Widget) Bit Description 7:3 Reserved. 2 L-R Swap. Not supported. Read as 0. 1 EAPD Enable. 0: EAPD pin state is not controlled by the power state of the corresponding pin widget 1: EAPD pin state is controlled by the power state of the corresponding pin widget 0 BTL Enable. Not supported. Read as 0. Note: All nodes except NID=0Fh and NID=10h will ignore this verb.
Codec Response in Set Command for all NID Bit Description 31:0 0's.
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ALC260(D) Datasheet
8.39. Get/Set Volume Knob Widget (NID=1Bh) (Verb ID= F0Fh/70Fh)
Table 72. Get/Set Volume Knob Widget (NID=21h) (Verb ID= F0Fh/70Fh) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=Xh Verb ID=F0Fh 0's Bit [31:8]=0's, Bit [7:0] is volume Codec Response for NID=1Bh (Volume Knob Widget) Bit Description 31:8 Reserved. 7 Direct. Not supported. Response will be 0 for this bit. 6:0 Volume in steps. Volume in steps is a sensed DC Voltage Code at the DCVOL pin. An integrated 6-bit ADC supports a maximum of 64 volume steps. Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response Format Response [31:0] 0's
Bit [19:8] Verb ID=70Fh
Payload Bit [7:0] Bit [7] is `Direct' control
`Payload' in Set Command for NID=1Bh (Volume Knob Widget) Bit Description 31:8 Reserved. 7 Direct. Not supported. This bit will be ignored. 6:0 Reserved.
8.40. Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Table 73. Verb - Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd = X Node ID=01h Verb ID=F20h 0s 32-bit Response
Codec Response for NID=01h Bit Description 31:16 Subsystem ID (Default=0260h). 15:8 Reserved. Read as 0's. 7:0 Assembly ID. Read as 0. Note: Not supported in the ALC260 and ALC260-LF. 2 Channel High Definition Audio Codec 62 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
8.41. Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 74. Verb - Set Subsystem ID [31:0] (Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0]) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd = X Node ID=01h Verb ID=723h, Label [7:0] 0s for all nodes 722h, 721h, 720h Note1: Supported by Audio Function Group NID=01h, other widgets will ignore this verb. Note2: The BIOS can use these verbs to set the customized sub-system ID for Audio Function Group (NID=01h). Note3: Not supported in the ALC260 and ALC260-LF.
Codec Response for all NID Bit Description 0s. 31:0
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ALC260(D) Datasheet
9.
9.1.
9.1.1.
Characteristics
DC Characteristics
Absolute Maximum Ratings
Table 75. Absolute Maximum Ratings Symbol Minimum Typical DVDD AVDD Ta Ts ESD (Electrostatic Discharge) Susceptibility Voltage 4500V 3.0 3.0 0 3.3 5.0 Maximum 3.6 5.5 +70 +125 Units V V o C
o
Parameter Power Supplies: Digital Analog Ambient Operating Temperature Storage Temperature
C
All Pins
9.1.2.
Threshold Voltage
Table 76. Threshold Voltage Symbol Minimum Typical Vin -0.30 VIL VIH VIL VIH VOH VOL 0.65* DVDD (2.00) 0.56* DVDD (1.85) 0.9*DVDD -10 -10 -
DVDD = 3.3V5%, Tambient = 25C, with 50pF external load.
Parameter Input Voltage Range Low Level Input Voltage (BCLK, RST#, SDO, SYNC, SDI) High Level Input Voltage (BCLK, RST#, SDO, SYNC, SDI) Low Level Input Voltage (S/PDIF-IN/OUT, GPIOs) High Level Input Voltage (S/PDIF-IN/OUT, GPIOs) High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current (Hi-Z) Output Buffer Drive Current Internal Pull Up Resistance Maximum DVDD +0.30 0.30*DVDD (1.00) 0.44*DVDD (1.45) 0.1*DVDD 10 10 100k Units V V V V V V V A A mA
5 50k
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ALC260(D) Datasheet
9.1.3.
Digital Filter Characteristics
Table 77. Digital Filter Characteristics Symbol Minimum Typical Passband 0 Stopband 28.8 Stopband Rejection -76.0 Passband 0.20 Frequency Response Passband 0 Stopband 28.8 Stopband Rejection -78.5 Passband 0.20 Frequency Response Maximum 19.2 Units kHz kHz dB dB kHz kHz dB dB
Filter ADC Lowpass Filter
DAC Lowpass Filter
19.2
9.1.4.
S/PDIF Input/Output Characteristics
Table 78. S/PDIF Input/Output Characteristics Symbol Minimum Typical VOH 3.0 3.3 VOL 0 VIH 1.85 VIL Vt 1.65
DVDD= 3.3V, Tambient=25C, with 75 external load.
Parameter S/PDIF-OUT High Level Output S/PDIF-OUT Low Level Output S/PDIF-IN High Level Input S/PDIF-IN Low Level Input S/PDIF-IN Bias Level Maximum 0.3 1.45 Units V V V V V
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ALC260(D) Datasheet
9.2.
9.2.1.
AC Characteristics
Link Reset and Initialization Timing
Table 79. Link Reset and Initialization Timing Symbol Minimum Typical TRST 1.0 TPLL 20 TFRAME Maximum 1 Units s s Frame Time
Parameter RESET# Active Low Pulse Width RESET# Inactive to BCLK Startup delay for PLL ready time SDI Initialization Request
4 BCLK
4 BCLK
>= 4 BCLK
Initialization Sequence
BCLK SYNC SDO SDI
Initialization Request Normal Frame SYNC
RESET#
TRST TPLL T FRAME
Figure 13. Link Reset and Initialization Timing
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ALC260(D) Datasheet
9.2.2.
Link Timing Parameters at the Codec
Maximum 2.0 22.91 (55%) 22.91 (55%) 8.0 Units MHz ns ns ns (%) ns (%) ns ns ns ns
Table 80. Link Timing Parameters at the Codec Symbol Minimum Typical 24.0 Tcycle 41.67 Tjitter Thigh 18.75 (45%) BCLK Low Pulse Width Tlow 18.75 (45%) Tsetup 2.1 SDO Setup Time at Both Rising and Falling Edge of BCLK Thold 2.1 SDO Hold Time at Both Rising and Falling Edge of BCLK Ttco 7.5 SDI Valid Time After Rising Edge of BCLK (1: 50pF external load) SDI Flight Time Tflight 2.0 Parameter BCLK Frequency BCLK Period BCLK Jitter BCLK High Pulse Width
T_cycle T_high
BCLK
VIH VT V IL T_setup T_hold T_low
SDO
T_tco VOH
SDI
VOL T_flight
Figure 14. Link Signals Timing 2 Channel High Definition Audio Codec 67 Track ID: JATR-1076-21 Rev. 1.3
ALC260(D) Datasheet
9.2.3.
S/PDIF Output and Input Timing
Maximum 4 84.6 (52%) 84.6 (52%) 10 89.5 (55%) 89.5 (55%) Units MHz ns ns ns (%) ns (%) ns ns ns ns ns (%) ns (%)
Table 81. S/PDIF Output and Input Timing Parameter Symbol Minimum Typical S/PDIF-OUT Frequency *1 6.144 *1 S/PDIF-OUT Period Tcycle 162.8 S/PDIF-OUT Jitter Tjitter *1 S/PDIF-OUT High Level Width THigh 78.1 (48%) 81.4 (50%) S/PDIF-OUT Low Level Width *1 TLow 78.1 (48%) 81.4 (50%) S/PDIF-OUT Rising Time Trise 2.0 S/PDIF-OUT Falling Time Tfall 2.0 *2 S/PDIF-IN Period Tcycle 162.8 S/PDIF-IN Jitter Tjitter *2 S/PDIF-IN High Level Width THigh 73.2 (45%) 81.4 (50%) S/PDIF-IN Low Level Width *2 TLow 73.2 (45%) 81.4 (50%) *1: Bit parameters for 48kHz sample rate of S/PDIF-OUT *2: Bit parameters for 48kHz sample rate of S/PDIF-IN
Tcycle Thigh VIH VIL Trise Tfall V OL Tlow VOH Vt
Figure 15. Input and Output Timing
9.2.4.
Test Mode
Codec test mode and Automatic Test Equipment (ATE) mode are not supported.
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ALC260(D) Datasheet
9.3.
Analog Performance
Tambient=25 oC, DVDD=5.0 or 3.3V 5%, AVDD=5.0V5% 1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms 10K/50pF load; Test bench Characterization BW: 10Hz~22kHz, 0dB attenuation
Standard Test Conditions
Table 82. Analog Performance Parameter Min Typ Full Scale Input Voltage All Inputs (gain=0dB) 1.6 All ADC 1.1 Full Scale Output Voltage All DAC 1.1 S/N (A Weighted) Analog Inputs to Outputs 95 ADC 90 DAC 95 THD+N Analog Inputs to Outputs -90 ADC -85 DAC -90 Frequency Response Mixers 10 ADC, DAC 16 Power Supply Rejection -40 Total Out-of-Band Noise (28.8kHz~100kHz) -60 Amplifier Gain Step 1 Crosstalk Between Input Channels -80 Input Impedance (gain=0dB) 64 Output Impedance Amplified Output 1 Non-amplified Output 200 Digital Power Supply Current (normal operation) DVDD=3.3V Digital Power Supply Current (power down mode) DVDD=3.3V Analog Power Supply Current (normal operation) AVDD=5.0V/3.3V Analog Power Supply Current (power down mode) AVDD=5.0V/3.3V VREFOUTx Output Voltage VREFOUTx Output Current 2.25 35 68/52 2.50 5
Max -22,000 19,200 -
Units Vrms Vrms Vrms dB FSA dB FSA dB FSA dB FS dB FS dB FS Hz Hz dB dB dB dB K mA A mA A V mA
47,000 600 600/400 3.75
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ALC260(D) Datasheet
10. Application Circuits
Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design and software driver, Realtek should confirm any modification of application circuits. Realtek may upload the latest application circuits onto our web site (www.realtek.com.tw) without modifying this datasheet.
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ALC260(D) Datasheet
11. Mechanical Dimensions
L L1
SYMBOL
A A1 A2 c D D1 D2 E E1 E2 b e TH L L1
MILLIMETER INCH MIN. TYP MAX. MIN. TYP 1.60 0.05 0.15 0.002 1.35 1.40 1.45 0.053 0.055 0.09 0.20 0.004 9.00 BSC 0.354 BSC 7.00 BSC 0.276 BSC 5.50 0.217 9.00 BSC 0.354 BSC 7.00BSC 0.276 BSC 5.50 0.217 0.17 0.20 0.27 0.007 0.008 0o 0.45 0.50 BSC 3.5o 7o 0.60 0.75 1.00 0o 0.018
MAX 0.063 0.006 0.057 0.008 TITLE: LQFP-48 (7.0x7.0x1.6mm) PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm LEADFRAME MATERIAL APPROVE DOC. NO. VERSION 02 CHECK DWG NO. PKGC-065 DATE REALTEK SEMICONDUCTOR CORP.
0.011
0.0196 BSC 3.5o 7o 0.0236 0.030 0.0393
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ALC260(D) Datasheet
12. Ordering Information
Table 83. Ordering Information Part Number Package ALC260 LQFP-48. HDA ver. 0.9 compliant ALC260-LF ALC260 with Lead (Pb)-Free LQFP-48 package ALC260-VD LQFP-48. HDA ver. 1.0 compliant ALC260-VD-LF ALC260-VD with Lead (Pb)-Free LQFP-48 package ALC260D ALC260-VD + Dolby(R) Digital Live (software feature) ALC260D-LF ALC260D + Lead (Pb)-Free LQFP-48 package ALC260-VE LQFP-48, HDA ver. 1.0 compliant (no PCBeep Pass-Through) ALC260-VE-LF ALC260-VE with Lead (Pb)-Free LQFP-48 package ALC260D-VE ALC260-VE + Dolby(R) Digital Live (software feature) ALC260D-VE-LF ALC260D-VE + Lead (Pb)-Free LQFP-48 package Note: See page 5 for lead (Pb)-free package and version identification. Status
Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel: 886-3-5780211 Fax: 886-3-5776047 www.realtek.com.tw
2 Channel High Definition Audio Codec 72 Track ID: JATR-1076-21 Rev. 1.3

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